DDR4 Problem Statement

A client brought a new design to us that included an embedded chip-down DDR4 memory controller. During hardware bring-up the memory accesses had been found to be unreliable, error-free on some days but barely operational on others. Performance seemed to be very dependent upon temperature and although down-clocking helped, it did not cure. This scenario is not uncommon with PCBs that were designed ‘to rule’. Effort had been made to keep signal paths consistent and matched for delay, but no simulations had been run to verify the final layout.

The Solution

The board was taken through our standard signal integrity analysis flow. Simulations were run to establish whether or not SI or PI (or both) were likely causes of poor performance. They were. The simulations took into account signal crosstalk, stack-up/materials, power supply noise, jitter, decoupling, power plane integrity, device packages… When all these factors were taken into consideration the tools provided a set of results that did not meet the JEDEC DDR4 specification. The DDR4 signalling and power delivery networks were re-routed following analysis. The simulations were repeated at the end of the design phase to verify the new layout. The design was then found to  meet the DDR4 specifications and the client committed to manufacture.

Through PVT testing, the resulting hardware was found to function correctly at full speed and with good headroom across variations in process, voltage and temperature.